Detecting the solar MPP on a cycle by cycle basis sounds like an interesting idea. If I understood, this sounds like a simple two state circuit. I quote "simple" because it sounds simple conceptually but I really have no idea how it would be implemented:
I believe that this approach not only adjusts the duty cycle to achieve the MPP boost but will also increase the PWM frequency at lower power levels (which I've taken to see as a good thing.)
How's that sound?
- Ed.[ Parent ]
Have fun, Scott.[ Parent ]
Design problems, Inductor has min and peak current, battery will see average current. Panel will deliver average current so inductor does not get "charged" up to peak current. By adding Cap on input fixes this. Problem inductor can 'take' more current for a while than the panel can deliver, making the software more complex. For a while did not think it had a solution. Figured it out... I think!-)
Hold on for another day or two OK?
But software? I thought you could do one this with an op-amp and couple of caps ... :-)
It will work. Monitoring only MosFET current. Intelligence is required to control for MPPT. Using your above circuit connected to a Microprocessor.
Current monitoring Analog switch to capture peak current in FET. Don't forget must Handle Boosted voltage!
Input capacitor to Inductor is required to supply peak current. Size the cap to limit voltage change to 30mv or less. C = i * delta(t)/delta(v) Delta(t) is PWM on time, delta(v) is the allowed voltage change. Battery side cap should be as large. On booster circuit board to limit EMI. Please note large cap's have leakage currents losses, don't make larger than needed.
ADC input Signal from MosFET is small, amplify it some. Target half ADC range for normal operations. 10 bits may be needed.
How to make it work? You have the math down for the boost converter. So not covered here. ADC must sample at the LC time constant or slower. Input Cap.
Set Ton time, watch current, going up, same, decreasing. Create a decision tree based on power curve and the Panels effects by being over loaded or under loaded. Code not looking too bad.
Due to input Cap, the inductor can draw extra current for a few cycles, that is why sample current at LC time constant rate, giving it time to respond to the new conditions.
If Ton is too long, the current will not keep going up. The driving force into the inductor is the voltage across it. See my above long posting. When the panel is over loaded the output voltage will drop, with same Ton will end with less current! Vary Ton to find Max current point. Constantly vary Ton to see if Max point has changed.
I sent this figuring you may want to get yours going while I work on mine!
Let me test my understanding...
C = 5 amps * .000008 seconds / .030 volts C = 1,333 uF
Since caps loose their uf over time, probably want larger value?
> Current monitoring - Analog switch to capture peak current in FET.
I'm not sure how an analog switch would do that but since R (isn't "R" = Rdson?) is fixed, isn't peak current at the same time as peak voltage... which would be just as the inductor is turned on? Then why not sample that with the micro's ADC?
> ADC must sample at the LC time constant or slower. Input Cap.
I google nil on LC time constant. Is that perhaps RC with R being the R of the coil or maybe LR with R being the R of the FET or do I need to keep looking for "LC"?
I'm guessing RC ... I'm using a JW Miller 2312-V-RC with a DCR of .037 ohms times .001333 farad = 49 uS. That's 20KHz or slower so that's okay.
Okay. I still think that peak current(FET voltage) will vary strictly with duty cycle but, if I understand, cap voltage will drop as the panel is loaded so cap volts times FET volts will vary as the power does and I can use that to direct towards MPP.
Well, I did go off track?
BTW, the reason that I keep hanging on to using the micro's ADC on the FET is that the timing of the sample and hold is very well defined and even though it has to be started before the PWM pulse, it can be scheduled to an accuracy of a single clock cycle. Also, while the aperture on the sample and hold is many clock cycles, the cap itself is only 14 pf (if I read the data sheet correctly) and I think (read "guess") that that will respond in sub-microsecond timing.
What do you think?
Thanks again! - Ed.[ Parent ]
I had made an error in my cap size, so suggested 0.03v thinking it would only be 10uf.
The current should be the panels current. Your test example above is few watts? Was the 5 amps the peak inductor current? Or do you have 85w panel just waiting to be used?
I would not use a cap that big. The voltage change can be larger than 0.03v, lets try it again with 0.1v to get a more reasonably sized cap. Like 400uf, much better. For over temp and life 470uf works. Assuming 5a and 8us. The cap only needs to supply the current when it exceeds the panels capability, which it must so the average current in the inductor is equal to the panels peak power point current:-) Realized inductors current is above the panels for less than half the time, the cap can be sized to half the above calculated. 250uf.
The ADC must be protected from the Battery voltage across the FET after it turns OFF. The FET's voltage should be captured just BEFORE it turns OFF. When Inductors current will be at its peak. If you can protect the ADC input and measure it at the right time then great! Do what ever works. Input voltage to ADC must NOT exceed its supply voltage.
LC time constant = square root (LC) After making a change to the on time (Ton) wait LC time constant before making a decision. The capacitor will supply extra current for a few cycles before the system stabilizes to the new condition. Looking too soon can miss lead you into thinking you can transfer more power than is available. Nothing wrong with waiting even longer, just don't want seconds to go by.
"Okay. I still think that peak current(FET voltage) will vary strictly with duty cycle" Go back and look at the panels output voltage vs current. Starting out the panels output is limited by the output voltage. As the load current increases the output voltage droops a little but is more or less constant. As the load exceeds the POWER capacity of the panel, the voltage crashes as the current is increased to the shorted condition. Without a cap before the inductor, when the inductor's current exceeds the panels current limit, the voltage will drop preventing the inductor's current from increasing, the inductor may give back...
The driving force for an inductor is Voltage. Using your inductor as an example, with 20v across it what will the current be in 8us? Then try that with 10v? Current will be half at the end of the same 8us.
Okay, I've been looking at the other part of the curve...
Here's an example of an inductor voltage(yellow) vs FET off time(purple) plot that my simple simulator shows: This is 17 volts in at 1 amp, 29 volts out, period = 20uS and duty cycle 50%
I think that the integration of the first part of the waveform is directly related to input power, if that can be done then no other sensors are needed for MPPT.
Also, no calculation would been needed for the off-time as the FET voltage drops to the input voltage as soon as it droops below the output voltage. (In this simulation, the FET is off for about three times longer than it should be.)
> The FET's voltage should be captured just BEFORE it turns OFF. When Inductors current will be at its peak.
Okay, I have to turn up the gain on my pretend o-scope to see the FET on-time... ... I think that you are saying that, with the proper sized cap, that I can use the current calculated from end of that curve times the voltage across the cap as the power calculation?
> If you can protect the ADC input and measure it at the right time then great! Do what ever works. Input voltage to ADC must NOT exceed its supply voltage.
Okay, what I was thinking of was putting a voltage divider in there to get the peak voltage below Vcc but then running it into the 20x gain stage. Not sure yet but am thinking that Vcc or less presented to gain stage might saturate the ADC at higher volts (but not blow anything) yet still amplify the lower voltages to get more accurate readings there.
I can schedule the sample and hold aperture on the ADC to the clock cycle and guess that with its 16pF capacitor that the value held will be the voltage very close to the end-time of the window. I haven't done the programing yet but think that by sliding the aperture across a few PWM cycles that I can super sample the discharge curve and get a fair digitization of it... just theory at this point.
> Was the 5 amps the peak inductor current? Or do you have 85w panel just waiting to be used?
I wish! In a nutshell, I hope to get a Harbor Freight panel set and test the three panels both in parallel and in series. I'm guessing that bucking will be better than boosting but would like both circuits to handle two or perhaps three sets of panels. I can't invest much in solar right now but think that 5 amps could conceivably be a lot of watts in the buck version ...
How does that sound?
I do not understand your plots. Need plots like: http://en.wikipedia.org/wiki/Boost_converter Please use this for a discussion:-) Fig 3 shows inductor current, input and output voltage, on / off time.
Inductor current should be ramping up with FET on. Output voltage boosted while FET is off, inductors current decreasing.
Output power = IV, with a fixed output voltage, by maxing current we max power. The inductor currents wave form is the same each time just maybe higher / lower. Therefore by maxing the peak = max power, only one sample is required. Exactness is not required, if all samples are acquired the same way, method needs to show relative size. If bigger shows up as bigger and vice versa, should be good enough.
Boosting maybe better. If series connected panels are exactly the same then same. My panels are not the same, expecting 15% more power by boosting each separately.
Bucking can be better if the voltage is high, thinner wire back to battery where its bucked down... Many ways to look at this!
What simulator are you using, do not recognize pictures.
I think we're looking at apples and oranges... er, coils vs. FETs. My toy-ish simulator only gives me a virtual DVM and virtual oscilloscope for analysis. Yes, if I put the leads across the coil, then I get results similar to fig.3.
I thought that we were going to measure the voltage across the FET? As I understand fig.3, the FET voltage isn't shown.... The plots I posted simulate the standard boost circuit with the o-scope ground on ground, channel one on gate and channel two on drain.
The duty cycle in this sim was 50% and is seen by the square waveform in red. The voltage on the drain-source channel (yellow) is at 10v/div when the FET is turned off and shows a quick voltage spike to 50 volts or more that trails off until the voltage drops below battery volts (about 30v), then it slams down to input volts (about 17 volts).
The second image shows the voltage across the FET when it is turned on. Channel two is set to 50mv/div to show the detail during this phase. ( The voltage looks flat in the first image but it's not, it's just lost in the larger voltage scale.)
If I understood your instructions, I am to measure the FET voltage just before the FET is turned off, that would represent the approx 150mV shown on channel two in the second image.
If I understood your instructions, the volts measured just before the FET is turned off would be multiplied by the voltage across the cap. Power = Vcap * Vfet/Rdson but R is constant for purposes of relative comparison so forget about it. Is that right?
That seems to represent maximizing power in from the solar panel. When you first wrote of measuring current by using Rdson as "the shunt", I assumed you meant on the output (battery) side. Based on that, I was suggesting that the "tall area" in the left hand part of the yellow waveform in the first image, starting just after when the FET gate is turned off until the voltage drops below battery volts represents the power that is transferred to battery. Now we're considering (Vds x Rdson) x Vbatt. Similar to the previous case, Rdson is fixed and can be dropped from the calculation but now Vbattery is constant for purposes of relative comparison so we can forget about it as well. All that leaves to consider is volts across the FET for as long as the diode is conducting. From what I've seen from a few different input-power setups, I'm suspecting the using the diode conduction time alone might be adequate to track the MPP... hm, "maximizing conduction time of diode with a pwm output" sounds like a good description for MPPT on a chip.
Do you have an analog solution? I know that many folk would prefer an analog solution but it seems hard for me to beat the functionality of a two dollar microprocessor chip.
Is this making any sense?
We are on the same page! Some clarifications: I assume Vcap is the capacitor on the Solar Panels side? Power = Vcap * (Vfet/Rdson) / 2, correct for the panel side. Inductor Current is a ramp must Divide by 2 for the average current:-) As the panel is loaded Vcap will change (a lot), therefore power is dependent on it. As you state Rdson cycle by cycle is the same (dependent on temperature)
The energy in the inductor is the same for the charging and discharging equations: Power = Vbat * (Vfet/Rdson) / 2 (if discharging current is a ramp) Since Vbat is constant only need to max Vfet to Max power! If discharging is not ramp not sure if valid comparison? Need to think about this. Time PWM cycle to keep some current in the inductor at the end of the cycle to get ramp. (As long as the load side conditions remain the same, expect OK to let current go to zero.) Then comparisons of peak currents are representative of more energy = more power. Power transfer with inductor current going to zero requires larger Peaks currents to get the same average. 4 = 8/2, if current goes from 2 to 6 = 4 same average current. Peak currents are the root of most problems in a switcher.
Timing the length of inductor output is more difficult than measuring Vfet once.
Do you have an analog solution? No, I could... Couple years ago saw a very complex circuit doing MPPT. Much more Costly. May have been in a patent. (where I go to learn how things work:-)
Have fun, Scott. [ Parent ]
> Timing the length of inductor output is more difficult than measuring Vfet once.
!!!
Can it be that simple? Timing the inductor output is free when using a 16 bit timer for PWM on the AVR micros. Simply set up the input capture unit to trigger on the analog comparator...
I'm going to restart this reply down at the bottom of the page; in thread-view mode we are so far to the right of the page that only little words will fit on the screen...[ Parent ]
