Okay, I think I'm close; I could see a p-fet charging the cap and then turning off to hold; do I need one of them high side drivers to use the same with am n-fet? I'll throw this in the simulator and see what happens...
> Not so free:-) Circuitry is required to detect the voltage above panel. What is this in parts? What does it cost?
Okay, no incremental cost because I want to make a charge controller as well. But for MPPT only, that'd be a buck for the micro plus 4 resistors to make the two voltage dividers. Add twenty-five cents more to move up to a temperature compensated charge controller.
RS08!? No.No.No.No. I went to Freescale on two designs because they cost less; used the RS's big brothers: a QT60 in a Zigbee radio and a GB80 on a remote sensor board. I probably popped 40% of the chips just programming them and half of what remained in use in the field. I usually got pins shorting to high current; not just on the I'm-not-an-EE boards that I designed myself but the OEM Zigbee radios boards I bought as well. Now I have to stock chips for repair. Makes me very skittish every time I put a BDM cable on one. They seem fragile to me (though I really do like CodeWarrior for development.)
Perhaps I don't have an ESD Best Practices procedure in place here but on the other hand, I've never burned an ATMEL chip unless it really, really deserved it and certainly never just by handling it or a board it was in.
> >thinking that MPP tracking based on targeting 70 or 80 percent > You could be right. Question most panes OCV is like 20v, loaded is 17v or 85%??
I think that a fix boost calculated to do 17v to 29v would work fine for good panels in full sun. I know there's some power in party-cloudy but I honestly don't know whether it's worth the extra dollar to get MPPT or not. One big advantage of spending a dollar for the micro, though, is that it can automatically optimize itself to different panels connected to it.
Having fun! - Ed.[ Parent ]
In my humble opinion is insane to not MPPT if the cost is a micro with some code. Even your first stab at it boosted power 21%! The micro cost a buck, can't get 1 watt solar cell for that little.
Thanks for the FYI about the Freescale micro. Dealing with ESD is not difficult. I noticed on the demo board a few parts not on their recommended circuits. Demo board is S08, been working great. Not using BDM yet.
Sample and hold: use the 2N7002 N-channel and cap nothing else.
Okay, no incremental cost... I do not think so. The panels voltage can change as batteries. Circuit needs to detect when Inductors output drops to panels. How you going to make this work? Interested to see your circuit. Do not do it unless your interested in humoring me or plan to use it. Expect it to be more complicated than the sample and hold... !-)
Yes, Having fun, Scott.[ Parent ]
> I will give you a hint, let you discover it, if cant then I will tell you? Parts are 2N7002 and 30nf cap.
Okay, I give...best I got is two FETs and a diode (and the cap). I can get one diode and a cap to hold the sample when the panel volts go higher than what is sampled but it my cap follows the panel voltage if it goes less than the sample. If I put a diode in to stop that, it cap never goes lower to a lower voltage so then I need another FET (and control line) clear it. And maybe a resistor to limit the current when I drain the cap... I can't touch an eighteen cent solution; I'm stuck at more than double that.
> Expect it to be more complicated than the sample and hold... !-)
If you mean more complicated software, it surely will be but I really like the idea of all the sensing being inside the FET; it's a very portable and reusable idea. I'll report one way or the other.
- Ed,.[ Parent ]
OK.
Power FET D connects to inductor, G to micro, S to ground. (as expected?) 2N7002 D connects to inductor, G to micro, S to 30 nF cap then cap to ground. S + cap node connects to ADC input on Micro. Cap will have power FET delta voltage across it.
Sample cap voltage anytime the gate is low (off) for the last sample. Do not sample when the gate is on.
Voltage delta across power FET is less than 1 volt. (Or somethings wrong) While FET is turned on, Vbat when off or Vpanel. 2N7002 is turned on by couple volts, cap is not much load at these speeds.
ADC with 10 bits resolves 5mv, should be enough, Or sample 4 times or more and average to enhance ENOB.
Simple!?
Have fun, Scott. [ Parent ]
