> I will give you a hint, let you discover it, if cant then I will tell you? Parts are 2N7002 and 30nf cap.
Okay, I give...best I got is two FETs and a diode (and the cap). I can get one diode and a cap to hold the sample when the panel volts go higher than what is sampled but it my cap follows the panel voltage if it goes less than the sample. If I put a diode in to stop that, it cap never goes lower to a lower voltage so then I need another FET (and control line) clear it. And maybe a resistor to limit the current when I drain the cap... I can't touch an eighteen cent solution; I'm stuck at more than double that.
> Expect it to be more complicated than the sample and hold... !-)
If you mean more complicated software, it surely will be but I really like the idea of all the sensing being inside the FET; it's a very portable and reusable idea. I'll report one way or the other.
- Ed,.[ Parent ]
OK.
Power FET D connects to inductor, G to micro, S to ground. (as expected?) 2N7002 D connects to inductor, G to micro, S to 30 nF cap then cap to ground. S + cap node connects to ADC input on Micro. Cap will have power FET delta voltage across it.
Sample cap voltage anytime the gate is low (off) for the last sample. Do not sample when the gate is on.
Voltage delta across power FET is less than 1 volt. (Or somethings wrong) While FET is turned on, Vbat when off or Vpanel. 2N7002 is turned on by couple volts, cap is not much load at these speeds.
ADC with 10 bits resolves 5mv, should be enough, Or sample 4 times or more and average to enhance ENOB.
Simple!?
Have fun, Scott. [ Parent ]
