There is more than what has been commented,

5.8 watts and you did not have, practically a heat sink which "assisted" to increase the dissipation to at least twice very fast, in few seconds.

The IN5819 may have blown because the L*di/ dt, allowing the Fets to go high in voltage and start avalanching the Drain Source area and soon overheating, this as guest by another member and by the possible high inductances in the setup.

Also, one needs to examine the whole system in reference with the current being drawn, items like the ground connection and its thickness and or length, in addition the way that the ground loop driving the gates is to the gate driving circuit.

The circuit I see, is a constant current ON and fast discharge OFF, which can allow the Fets to stay a bit too long going ON during the time going to Full ON.

The Gate driving circuit is somewhat high impedance going ON, it should have the NPN upper transistor converted to PNP and the proper polarity of the signal modified and in this case move the LED to the output of the Gate driving circuit.

Also, add two 1N5819 diodes in series anti parallel with the center connected to the junction of the Grate driving circuit to protect the circuit from avalanching if the Mosfets have a lot a Miller Effect behavior and the driving circuit can not handle the high back current pulse

There are other points, like I said at the beginning, connect with me directly.

At dump time, assuming 30v, ( I know you tested at 25v, but you'll be dumping at around thirty in real life I suspect) depending on your pwm pulse width, you may be switching up to 1500W into your .6 ohm load. In other words, about 50A at full pulse width. For the heatsink you have, it may prove possible if the wave form is perfect, there is no rise time (it is perfect) and full saturation is reached instantly.

In the real world, this is hard to achieve.

Firstly I would bring your resistor array up to about 6ohms for testing. This should limit your power to 900/6 =150W which your configuration should handle even if your switching wave forms are not perfect.

This next part I wrote before you posted your response so is probably of little use, but i'll leave it in anyway:-)

[Then get the scope out and check your input to the fet waveforms, and the output wave forms.

If there is any sagging in the input waveform, it is what is introducing the losses in the fet, as it is spending too much time in amplification made rather than saturated mode.

If the input is a perfect square wave, but the output has slopes rather than vertical rises, then saturation is incomplete, and the losses in unsaturated mode will show up as rise lines with slope.

If the latter is the case, you may be getting some voltage drop from the totem pole driver from your 10v source, and you may need to use a 7812 to give you the drive voltage instead of your 10v reg.

If all appears to be good, (and you have fixed any waveform problems) the fets should run barely warm.

Start adding resistance and check your waveforms. If the waveforms  start to fail, you'll need to find out why.]

You may have to adjust your pulse width maximum to keep within the bounds of how much heat sink you are going to use, but if you want to dump all at once at 1500w, you'll need a swag more than you have. If you keep below 200W, you probably have enough..... providing you have a good waveform.

The freewheel diode needs to handle the back EMF peaks, but at 2k5hz it should be ok... maybe increase it's voltage and current rating as Samoa suggests. I don't think it is what failed in this instance, but you will know that by now anyway. (was it?).

Poor waveform could be being developed by T3 and T4.  and the led hanging on the same line. A scope would help here.... but test the array with and without this added non-linear load (the LED)... You may find that the LED will load the pulse train up as it's increases in brightness with the pulse width. This will warp the pulseby loading the output from your pic.

The buffer trannies.....Perhaps bypass these so the pwm drives the totem without a buffer, and run again. Increasing the load and checking temp etc.... (I havent used pics to drive fet arrays before, so am not sure of the ramifications of this procedure so be wary of this advice), but if output is clean at the pic, the only other waveform polluter I can see is this pair of trannies, and the dumping led display on the same line.... Testing testing and more testing may show up the culprit.

This may not be too helpful, but may give you something to work with. No scope makes this a suck it and see procedure, so protect the output stage by going up slowly (pulse width and load) and document what changes as you increase power output.

A well shaped and saturated array will run surprisingly cool, but the slightest deviation from perfect waveform will rapidly erode efficiency.

gotta go now

  I'm currently designing an induction furnace (long story, not related to anything on this board other than using IGBT's and FETS), but here's some good FET design advice, from a guy who has watched $35 IGBT's explode like little fragmentation grenades...

#1.  Use dedicated gate-drive chips.  I prefer the Texas Instruments TC4420/TC4429 complementary chips in a half-bridge configuration.  One is inverting, so one logic signal controls both chips.  The output of the half bridge drives a gate drive transformer.   What's that?   It's a toroidal ferrite core, wound with 10-12 primary turns, and usually a 1:2 ratio, with as many secondaries (one secondary per FET) as necessary.  A single TC4420/TC4429 half bridge can drive 4 beefy FETs at a 100khz with ease.  At more than 100khz, or more than 4 fets, add more gate drivers in parallel.  One lead of each secondary goes to a FET source, the other to the gate, with a 10 ohm 1W resistor in series between the secondary winding and the FET gate.  This damps the parasitic oscillations caused by the inductance of the gate transformer and the gate capacitance.  The gate drive transformer should put out about 28-30v pk-pk.  The gate drive xformer also isolates your control electronics (read, expensive PIC processor) from the brute force of the supply rails (read, your battery bank shorting out through our PIC processor if a FET fails gate-to-drain).

#2.  Use back to back zeners from the gate to source of the FETS to clamp the gate drive voltage to a safe level.  I use 3 or 5 W zener diodes, generally two 12 or 15v zeners back to back.   This prevents over-volting the FET gates, but the higher gate drive voltage really decreases the switching time for the FET, ensuring it's acting as a switch, and not an amplifier.

#3.  ENSURE ALL LEADS TO ALL FET PINS ARE THE SAME LENGTH!!!!!   This ensures that the inductance for each gate/source/drain lead is the same!  This is not super-important at the low frequency you're running at, but it's good design practice and keeps switching times closer between all the FETs.  Extra length = more inductance = switching time is different = one fet turns on before the others and must carry more load.  That could equal a loud bang, and a puff of smoke.  

#4.  Eliminate any unnecessary inductance from the load.  Inductance + fast switching (to keep FET heating down), + big currents = high voltage spikes at turn on and turn off.  An ultrafast diode and a Schottky diode on each fet drain-source will bypass the very slow built in diode and protect the FET itself from the big voltage spikes.  By bypassing/isolating the internal FET diode, it doesn't freewheel conduct during the large voltage spikes.  Saves on FET heating a bit.  Though, at the frequency you're running at, the FET internal diode may be fast enough to catch the spikes.  

#5.  Place low ESR capacitors across the fet source/drain.  Scrounge these from computer switching power supplies.  This helps soak up the voltage spikes at the FET.  Don't use electrolytic, as most of them tend to get cranky about high ripple current.  
Use poly film or metallised poly film. Polypropylene is best, mylar (polyester) will work okay for the frequency you're running, but don't run it at any substantial power level at a frequency greater than 50-80 khz.  Mylar is lossy at high frequency.

#6.  Keep in mind that FETS dissipate the most power while switching as they transition from high to low resistance, or vice-versa.  Since you're not switching a resonant circuit, the FET appears as a very fast potentiometer between the load and the supply.  Anywhere between "nearly infinite ohms" and "Nearly zero ohms", it's just a resistor, and as such, dissipates heat.  Heat is also generated by charging and discharging the gate capacitance, but again, at the low frequency you're running at, it should be a trivial amount.  

Hope it helps!

Shad H.

Not much time today. So will be very direct.
Worried about inductance of the wiring between the battery and your box.
Not the load. You have it covered by the diode.

The cap goes across the pos side of the load AND the FETs ground.
Where Vbat comes into box CAP across pos and neg.

40 in of wire = 1.5uH inductance. Free space single conductor. CRC manual.
The wider the pos and neg wires are apart the more inductance it will have; 2-3x more. The pos and neg are wires each and both add to the effect.
This equates to 11 feet of wire from battery and your box.

Hard to believe you have less then 10uH in your system wiring. Or have short wires.
The higher freq reduces the inductance you need down to 3uH which is only 4 feet of wire.

If you can afford the risk of replacing the FET try it with the Cap AS is. You may be surprised it will work.

Sorry about the delay, did not see your reply until now.
No email address to send to get your attention sooner...

Bigger caps are fine. I mentioned the ATX supply because they're low ESR caps and are big uF, high voltage and current. And, I figured you had some!
You want a low ESR cap, the only reason I mentioned several was to get effective low ESR.
Yes - use: "The big ones are electrolytic, about 360uF 200v." One should do it.

If the cap is doing its job, it will be self limiting the voltage seen, my calculation limited the voltage to 40v so a 50v cap would be fine. Can you get 36uf or more at 50v?
How many will you be building?