Confused by FET smoke and fire

[elt]

I built and programmed my PWM dump load controller discussed in the other thread

(http://www.fieldlines.com/story/2007/7/5/172519/4320)

Here's a pic...

Right now it's programmed as a bang-bang controller with a soft start. (The PWM duty cycle ramps up over a two second period.) For testing purposes, I programmed the button push to do a ten second dump.

I did my initial testing and it worked very well at 10 and 20 volts with a 20 ohm load.

I installed it on my 24v battery bank bank with its .6 ohm load and pushed the button. It made it through about 1/4 of its ramp up and the LEDs went out... I pushed the button a few more times and eventually held it down; one of the FETs desoldered itself and started to sag on the board... I disconnected it and brought it back in.

I don't know how to test FETs but the one that sagged gave me a 1 voltage drop reading on its while the rest gave 1.3 volts which was about right...

BTW, I'm using stp60nf06's

http://www.st.com/stonline/products/literature/ds/7559/stp60nf06.pdf

I took a guess that the 5.5v 100 ma regulator was browning out and the causing the processor to continuously reset; the only thing I had of higher power (3 amps) was 5v, so I put that in. Again, it worked great with the lighter load inside. When I put it on my dump load, it didn't do anything... (and I didn't continuously hold down the dump button this time, I'm slow but I can learn!)

Again, I assume that the switching current is browning out the voltage regulator making  the processor continuously go into reset. Because the dump cycle didn't even appear to start I thought maybe I really do need a higher gate voltage.

I rewired the vreg for 10 volts and dead-bugged a level shifter and 5 volt regulator for the processor onto the board.

Again, worked great inside. On the mill, I was pleased to see the 10 second dump cycle start, run and finish and reached to put my hand on the FET heatsinks to see if they were warm and burned my finger. About a second later, smoke started leaking and another second later the board burst into flames.

Looking at it after I blew the fire out I saw that one FET desoldered itself, another melted off a pin and one exploded (and caught fire.)

I brought it inside, cut off the FETs and the digital section, voltage regulators and FET drivers still work! The only thing that was out of norm was the the 1n5819 I put in for a catch diode was conducting, acting something like a 4 volt zener... I think that's a casualty rather than a cause though, I can't see that package not breaking open if it was shorting the drains...

Here's the latest schematic -

I thought I was close but I'm stumped... any ideas?

- Ed.

[Nando]

ERROR NUMBER ZERO :

I recommended higher than 5 volts, like 10 volts

Did you install a resistor for each Gate ?.

How fast the Gate switching was done ( rise and fall times).

Error Number one:

You used 5 volts for the gates, YOU Need at least 10 volts, or "many" Fets in parallel

Error Number two:

Poor Heat sink, you should have a large heat sink, Unless you know how to calculate dissipation and know how the Fets operate.

One Once of prevention is better that one pound of cure.

third:

The supply voltage needs to be stable and ALWAYS above the minimum that the gates require for full saturation

How to test FETS : place a short from Gate to Source, then with an Ohmmeter, positive lead to Drain and negative lead to Source TO READ AROUND ( low ohms) then Reverse the leads TO READ HIGH OHMS.

Also: to test, take a 9 volts battery (or isolated supply), place a resistor in the positive leads, 1k to 10k ohms Ok, connect the positive lead of a Voltmeter to the opposite end of the resistor and the negative lead of the meter to the negative of the supply.

Then with the gate shorted to the Source, place positive lead to DRAIN and negative lead to Source, the full voltage of the battery used for testing the MosFet, reverse the leads connection to the Fet and you should read the intrinsic diode voltage ( around 0.4 to 0.7 ) Volts.

To test the Gate, make a small amplifier circuit, using some resiStance like 1k OHMS to a 12 volts supply, then place a 47 K ohms from the gate to the source, read the drain-source voltage, then place a positive voltage like 6 to 10 volts Gate to Source the Drain should show almost zero volts if the MosFet is OK.

Nando

[s4w2099]

you have an oscilloscope? check the PWM signal to see that its clean going from 0V to 10 and the rise and fall times are very short. Remember for power applications FUSES are your friends.

What is the frequency?

[elt]

Hi Nando, I appreciate the reply.

I apologize but I think most of your comments are based on looking that the wrong schematic. I uploaded two and you likely won't see the second one unless you do a page reload. Here it is again, it's more legible linked indirectly where it is not squished-

http://www.otherpower.com/images/scimages/6527/DumbBoard_3s.gif

(If you don't see 10 volt drives, you need to do a "page reload.")

The Rdson is given as .014 ohms. With six devices and a 50 amp load, I was calculating that each FET was only be dissipating about a watt. (.014/6 * 50 * 50 = 5.8 watts total for six devices.) I didn't do any temperature derating because I didn't think they'd heat up that much! ... am I doing that incorrectly?

Thanks again,

 - Ed.

[s4w2099]

add to that a big capacitor across the micro controller power supply. That chip must be reseting badly.

[SamoaPower]

elt,

I suspect the 1N5819 was actually the cause. It's rated at 1A and 40V. Depending on the inductance of your load and wiring, the spike voltage can get quite high with a fair amount of peak current during fast switching. If the diode fails shorted, you lose the current limiting of the load to the FETs and no doubt they will go poof.

I'd suggest a fast or ultrafast type rated at least a few hundred volts and 3A minimum.

[stephent]

The load is in parallel with the FET's?

[elt]

A fuse... really? I thought about a fuse but I didn't know where I'd put one. When I did the test, the bank was only at 25.3 volts and the dump load is about .6 ohm ... 42 amps. The current can't get higher than I = V/R and the circuit needs to hand that, whatever it is, so I don't know what I would fuse. I guess that dump could short out but that didn't happen this time. (The dump was slightly warm so I know the current was going through it.)

Right now the PWM is programmed for 2.5 KHz. Its programmable from 64 MHz on down; what would you suggest?

Unfortunately, I don't have an o-scope right now I don't know where I'd get my hands on one. The rise/fall time for the transistors is given as 20/30 ns. The processor pin rise time is given as (20 + .1C)ns where C is the line capacitance in picofarads with a maximum of 250 ns.

Even so, I'm assuming I'm not turning the FET's on "hard." If I did have an o-scope and I saw slow rise times, where would I look to for the cause?

Or, if I did see nice waveforms, where would I look then?

Thank you,

- Ed.

[RP]

Something to consider in your board layout.  When the Fets go into conduction they not only pull the positive battery rail down with the dump load, they also pull the ground rail upward.

Take a look at your layout and circuit from the perspective of "what happens if my ground gets pulled up by a volt or three".  I know I've been bitten by this before.

[scottsAI]

Hello elt,

Very interesting, almost defies logic! Almost.

First look, everything looks like you did it right.

Even second look, circuit looks good. Little over kill with the number of Fets.

So why did it fry?

With a 0.6 ohm load, the current is 43 amps. (assuming 26v battery)

Spread across 6 Fets at 7+ amps each, Rdson = 0.016 ohms, less than 1 watt.

Well within the Fets ratings. Even 10x that with the heat sinks attached should not be a problem.

Dodie has damage, not destroyed like it was fried.

Yet, Several Fets get fried.

Unit worked with a smaller load... but not with a larger one.

Something else changed. What was it?

Here's the answer:

The problem is inductance in the wiring from the battery to the diode, the PWM load creates a voltage booster. The energy stored in the inductance is what will be frying stuff.

The Dodie ONLY protects for inductance in the LOAD. Not the problem here.

The boosted voltage is higher than the diodes reverse voltage rating and the Fets voltage ratings.

Every Fet will have a different break down voltage, thus only one or couple get fried.

The diode is getting fried, but slowly. Most likely after the Fets start frying.

Wiring inductance is not high, but enough watt/s (energy) is stored to burn the Diode and Fets.

Energy stored = L * ( I^2) / 2

Lets say L = 10uH, so the stored energy is 0.01849 joules Not much or is it?

This energy is released each PWM cycle.

PWM rate at 1kHz? This becomes 18 joules/s or 18 watts.

I suspect you have more inductance or higher PWM rate

As a guess to fry the 3 fets, I would expect you to need about 10 w each.

10w would exceed the heat sinks you have. As the Fets get hot their leakage currents goes up adding more heat finishing the frying job.

The Fets are rated at 60v the break down will happen above this, 80-120v likely range.

The Fix:

You need to keep the voltage spike below the rating of the Fets and diode. Or below 40v.

A 36uf cap will do the job. If we allow 10v rise in voltage; solve for C

Stored energy = C * ( V^2) / 2

This energy will be dumped into the cap very fast, need a very low ESR cap as used in a switching power supply. Grab the big ones from a PC power supply. The initial charging current will be 43 amps, drops off very fast. So wire accordingly. Several caps in parallel give a lower ESR.

Check the Data sheet of the 5v regulator, most require more than 0.1uf, I would put no less than 10uf.

Some Data sheets lye, say only 0.1uf is required, look over all the application circuits, they show much more.

Technically the diode should be rated for the current in the load if your trying to protect from inductance in the load circuit. Grant you if inductance is low the initial spike may be 43 amps lasting only a few micro seconds, not enough to destroy the diode of a lesser rating.

I hope you find this useful, took about 4 hours!

Have fun,

Scott.

[oztules]

Hi Elt

At dump time, assuming 30v, ( I know you tested at 25v, but you'll be dumping at around thirty in real life I suspect) depending on your pwm pulse width, you may be switching up to 1500W into your .6 ohm load. In other words, about 50A at full pulse width. For the heatsink you have, it may prove possible if the wave form is perfect, there is no rise time (it is perfect) and full saturation is reached instantly.

In the real world, this is hard to achieve.

Firstly I would bring your resistor array up to about 6ohms for testing. This should limit your power to 900/6 =150W which your configuration should handle even if your switching wave forms are not perfect.

This next part I wrote before you posted your response so is probably of little use, but i'll leave it in anyway:-)

[Then get the scope out and check your input to the fet waveforms, and the output wave forms.

If there is any sagging in the input waveform, it is what is introducing the losses in the fet, as it is spending too much time in amplification made rather than saturated mode.

If the input is a perfect square wave, but the output has slopes rather than vertical rises, then saturation is incomplete, and the losses in unsaturated mode will show up as rise lines with slope.

If the latter is the case, you may be getting some voltage drop from the totem pole driver from your 10v source, and you may need to use a 7812 to give you the drive voltage instead of your 10v reg.

If all appears to be good, (and you have fixed any waveform problems) the fets should run barely warm.

Start adding resistance and check your waveforms. If the waveforms  start to fail, you'll need to find out why.]

You may have to adjust your pulse width maximum to keep within the bounds of how much heat sink you are going to use, but if you want to dump all at once at 1500w, you'll need a swag more than you have. If you keep below 200W, you probably have enough..... providing you have a good waveform.

The freewheel diode needs to handle the back EMF peaks, but at 2k5hz it should be ok... maybe increase it's voltage and current rating as Samoa suggests. I don't think it is what failed in this instance, but you will know that by now anyway. (was it?).

Poor waveform could be being developed by T3 and T4.  and the led hanging on the same line. A scope would help here.... but test the array with and without this added non-linear load (the LED)... You may find that the LED will load the pulse train up as it's increases in brightness with the pulse width. This will warp the pulseby loading the output from your pic.

The buffer trannies.....Perhaps bypass these so the pwm drives the totem without a buffer, and run again. Increasing the load and checking temp etc.... (I havent used pics to drive fet arrays before, so am not sure of the ramifications of this procedure so be wary of this advice), but if output is clean at the pic, the only other waveform polluter I can see is this pair of trannies, and the dumping led display on the same line.... Testing testing and more testing may show up the culprit.

This may not be too helpful, but may give you something to work with. No scope makes this a suck it and see procedure, so protect the output stage by going up slowly (pulse width and load) and document what changes as you increase power output.

A well shaped and saturated array will run surprisingly cool, but the slightest deviation from perfect waveform will rapidly erode efficiency.

gotta go now

......oztules

Flinders Island Australia

[Nando]

Why don't you send to me your Email address, correct mine for the anti-spam protection removal.

There is more than what has been commented,

5.8 watts and you did not have, practically a heat sink which "assisted" to increase the dissipation to at least twice very fast, in few seconds.

The IN5819 may have blown because the L*di/ dt, allowing the Fets to go high in voltage and start avalanching the Drain Source area and soon overheating, this as guest by another member and by the possible high inductances in the setup.

Also, one needs to examine the whole system in reference with the current being drawn, items like the ground connection and its thickness and or length, in addition the way that the ground loop driving the gates is to the gate driving circuit.

The circuit I see, is a constant current ON and fast discharge OFF, which can allow the Fets to stay a bit too long going ON during the time going to Full ON.

The Gate driving circuit is somewhat high impedance going ON, it should have the NPN upper transistor converted to PNP and the proper polarity of the signal modified and in this case move the LED to the output of the Gate driving circuit.

Also, add two 1N5819 diodes in series anti parallel with the center connected to the junction of the Grate driving circuit to protect the circuit from avalanching if the Mosfets have a lot a Miller Effect behavior and the driving circuit can not handle the high back current pulse

There are other points, like I said at the beginning, connect with me directly.

Nando

[elt]

I really appreciate all the help from everybody! I have to order another handful of FETs so it'll probably be the end of the week before can try again.

It's clear that the little 1n5819 has failed but it doesn't look like it shorted as the little 16 mil traces connecting it are still pristine. I'll replace that with a chunkier diode.

Using the air core inductor formulas, I can see each of the power resistors having up to a few uH of inductance but that gets divided by 12 with the 12 devices so I figure the load inductance is on the order of .1 uH ... not that I know what to do with that number now that I have it!

I don't know how I'd get 10 uH in the wiring from the diode to the battery+ (other than through the load.) Using my best imagination I can on guess two loops in that wiring.

... I'm not sure where you're suggesting I put the cap, parallel with the catch diode?

BTW - The PWM frequency is actually 3.8 KHz. Sounds like the FETs would be happier with a lower frequency but what would be good?

As to some of the other ideas - yes, the ground to the driver pair is a mess. It's the longest circuit on the board... I'll give that connection priority to the ground bus when I re-do the board.

I'm also thinking of using the microchip FET driver suggested now that I've given up on driving the FETs with 5-ish volts. Mouser, where I'm getting the FETs from, has it in stock in the to220-5 package and I think that'll be easy to slip into the board layout.

Thanks again!

- Ed.

[elt]

> Also, add two 1N5819 diodes in series anti parallel

> with the center connected to the junction of the Gate driving circuit

I'm not sure I can picture what you mean by this...



   --|<--

  |        |

----->|---- FET gates?




Thank you,

- Ed.

[Sundog]

The FETs you're using should be perfectly happy it the very low khz frequency they're seeing.  Heck, that's in the audible range.  

  I'm currently designing an induction furnace (long story, not related to anything on this board other than using IGBT's and FETS), but here's some good FET design advice, from a guy who has watched $35 IGBT's explode like little fragmentation grenades...

#1.  Use dedicated gate-drive chips.  I prefer the Texas Instruments TC4420/TC4429 complementary chips in a half-bridge configuration.  One is inverting, so one logic signal controls both chips.  The output of the half bridge drives a gate drive transformer.   What's that?   It's a toroidal ferrite core, wound with 10-12 primary turns, and usually a 1:2 ratio, with as many secondaries (one secondary per FET) as necessary.  A single TC4420/TC4429 half bridge can drive 4 beefy FETs at a 100khz with ease.  At more than 100khz, or more than 4 fets, add more gate drivers in parallel.  One lead of each secondary goes to a FET source, the other to the gate, with a 10 ohm 1W resistor in series between the secondary winding and the FET gate.  This damps the parasitic oscillations caused by the inductance of the gate transformer and the gate capacitance.  The gate drive transformer should put out about 28-30v pk-pk.  The gate drive xformer also isolates your control electronics (read, expensive PIC processor) from the brute force of the supply rails (read, your battery bank shorting out through our PIC processor if a FET fails gate-to-drain).

#2.  Use back to back zeners from the gate to source of the FETS to clamp the gate drive voltage to a safe level.  I use 3 or 5 W zener diodes, generally two 12 or 15v zeners back to back.   This prevents over-volting the FET gates, but the higher gate drive voltage really decreases the switching time for the FET, ensuring it's acting as a switch, and not an amplifier.

#3.  ENSURE ALL LEADS TO ALL FET PINS ARE THE SAME LENGTH!!!!!   This ensures that the inductance for each gate/source/drain lead is the same!  This is not super-important at the low frequency you're running at, but it's good design practice and keeps switching times closer between all the FETs.  Extra length = more inductance = switching time is different = one fet turns on before the others and must carry more load.  That could equal a loud bang, and a puff of smoke.  

#4.  Eliminate any unnecessary inductance from the load.  Inductance + fast switching (to keep FET heating down), + big currents = high voltage spikes at turn on and turn off.  An ultrafast diode and a Schottky diode on each fet drain-source will bypass the very slow built in diode and protect the FET itself from the big voltage spikes.  By bypassing/isolating the internal FET diode, it doesn't freewheel conduct during the large voltage spikes.  Saves on FET heating a bit.  Though, at the frequency you're running at, the FET internal diode may be fast enough to catch the spikes.  

#5.  Place low ESR capacitors across the fet source/drain.  Scrounge these from computer switching power supplies.  This helps soak up the voltage spikes at the FET.  Don't use electrolytic, as most of them tend to get cranky about high ripple current.  

Use poly film or metallised poly film. Polypropylene is best, mylar (polyester) will work okay for the frequency you're running, but don't run it at any substantial power level at a frequency greater than 50-80 khz.  Mylar is lossy at high frequency.

#6.  Keep in mind that FETS dissipate the most power while switching as they transition from high to low resistance, or vice-versa.  Since you're not switching a resonant circuit, the FET appears as a very fast potentiometer between the load and the supply.  Anywhere between "nearly infinite ohms" and "Nearly zero ohms", it's just a resistor, and as such, dissipates heat.  Heat is also generated by charging and discharging the gate capacitance, but again, at the low frequency you're running at, it should be a trivial amount.  

Hope it helps!

Shad H.

(no, I'm not an EE, but I did stay in a Holiday Inn Express once!)

[DamonHD]

Hi,

Not to hijack this thread, but I was asking over in this thread...

http://www.fieldlines.com/comments/2007/6/28/17204/5642/18#18

For a simple 12V nominal low-voltage drop-out circuit with a P-channel (ie high-side) FET power switch is it going to be enough/OK to pull down the gate with an open-collector output (~35mA max) and pull it up again with a resistor (say 1K to 10K)?

(I do intend to clamp the load output with a transient suppressor diode (~16V) to catch back EMF/spikes high and reverse, BTW.)

Rgds

Damon

[s4w2099]

Yeah, just as oztules said for testing you could use a higher resistance dump load. With an oscilloscope you would be able to see if your ACTUAL rise/fall times are in a tolerable range. The fuse would go in the high current side of the input (thats were the batteries connect to your controller. Having fuses would prevent board fire but that wont guarantee that your components will survive failure.

I dont know the length of the wires that you are using to hook all this up together but make sure to make them as short as possible or the inductance in the cables could cause spikes that might kill the mosfets and control circuitry. Ive had that problem A LOT in my electronics and it is not so obvious. This is accentuated with higher frequency.

[scottsAI]

Hello elt,

Not much time today. So will be very direct.

Worried about inductance of the wiring between the battery and your box.

Not the load. You have it covered by the diode.

The cap goes across the pos side of the load AND the FETs ground.

Where Vbat comes into box CAP across pos and neg.

40 in of wire = 1.5uH inductance. Free space single conductor. CRC manual.

The wider the pos and neg wires are apart the more inductance it will have; 2-3x more. The pos and neg are wires each and both add to the effect.

This equates to 11 feet of wire from battery and your box.

Hard to believe you have less then 10uH in your system wiring. Or have short wires.

The higher freq reduces the inductance you need down to 3uH which is only 4 feet of wire.

If you can afford the risk of replacing the FET try it with the Cap AS is. You may be surprised it will work.

Over all the frequency your working with does not require some of the other suggestions.

Your circuit as is should have worked. So something else is going on. No other suggestions fits the effects you reported QED.

Have fun,

Scott.

[elt]

> The higher freq reduces the inductance you need down to 3uH which is only 4 feet of wire.

I think the describes it fairly well, about four feet of #4 wire to the dump load...

Yes, I'll try the cap. Flux had me put in one on my MPPT booster and it's held up well (though it hasn't seen and won't see as much current as the dumper.) ... sound like I can easily halve the PWM frequency as well.

Thanks again,

- Ed.

[RobC]

Even In a best case scenario those fets will still produce heat and the heatsinks in your picture in my opinion aren't even close to whats required. At least thats what I have found from personal experience. For what's its worth RobC      

[scottsAI]

Hi RobC,

I was concerned about that, looked up the FET spec.

0.016 ohm, with 6 FETs at 43 amps = 7 amps each.

P = I * I * R = 49 * 0.016 = 0.749 watts, well within the capabilities of the heat sink shown!

That is assuming continuous, PWM must consider the duty cycle.

I am assuming the heat sinks are open to air? 0.749 w * 6 = 4.7 watts, will need some air.

The FETs according to DS can handle 60a, just two with a larger heat sink should be all that is necessary. By using more FETs virtually eliminates the heat sink.

Have fun,

Scott.

[Nando]

Diodes in series santiparallel

                     to Gate of Fet

                     >

                     <   Gate resistor

                     |

...(+voltage)----[<----[<---- ( - voltage )

                     |

                     |

                 ( gate driver

I hope this sketch passes the "word Processor " of Yahoo

Nando

[Nando]

It did not pass Yahoo word processor

Diodes in series antiparallel

                          to Gate of Fet

                          >

                          <   Gate resistor

                          |

...(+voltage)----[<----[<---- ( - voltage )

                         |

                         |

                    ( gate driver)

I hope this sketch passes the "word Processor " of Yahoo

The connections to the gate resistor and the Gate driver needs to go where the two diodes connect ( anode of one and cathode of the other).

Nando

[DamonHD]

Sketch it on a piece of paper and scan it in for us?  I'd very much like to see this!

Rgds

Damon

[Nando]

I have drawn the Series- Anti-Parallel circuit and saved in two formats to see what is best to display.

Nando

[elt]

I can understand that... thanks!

[ghurd]

That's assuming they all switch at exactly the same speed and time.

The fastest one gets the most heat.

Which is why I suggested he separate the quantity of resistors into individual smaller banks, each fed from a single fet.

G-

[scottsAI]

Hi ghurd,

In a high speed switching power supply the balancing of the FETs is important.

Here the 3.xx kHz lets call it 250us PWM rate is not an issue for several reasons.

One FET could handle the power, sharing it across 6 reduces the stress further.

One FET with the appropriate heat sink. (30 watts of heat)

The switching time vs on time is tinny.

Lets say 5us on time. (Would be excessively long time.) with 2 us of variation across the FETs for turn on: 2us / 125 (50% duty cycle) is less than 1 % time unbalanced.

High speed switch mode power supplies will have cycle times below 5us, so the imbalance could be a huge percentage of the on time creating a substantial imbalance in the FETs heat. Following the proper balancing methods is absolutely required... Also assuming the power was large enough to require multipliable FETs. Both not the case here.

Thus my comment about not needing to do some of the other things!

How does that sound to you?

Have fun,

Scott.

[ghurd]

I just got off a plane and am a bit fuzzy.

I believe most of the heat comes during switching, and anytime it is linear is bad.

The dump load (in this case) can be separated into 6 banks of 2 resistors.  Two resistors for each fet.

The maximum dump load amps for each fet is then controlled by the dump load itself.

No fet can see higher than expected amps, regardless of reaction time or switching speed.

Hard switching and separate loads for each fet should make all the other issues almost irrelevant?  

("I just got off a plane and am a bit fuzzy")

G-

[elt]

Hi Scott,

I really appreciate the analysis.

I'm confused about the caps you recommend. You wrote:

The Fix:

[...] A 36uf cap will do the job. [...] Grab the big ones from a PC power supply. [...] Several caps in parallel give a lower ESR.

I opened up a PC power supply I have and looked around. The big ones are electrolytic, about 360uF 200v. If I parallel them, I get even more uF. There are some blocky ones that I'm guessing are polyester or equivalent, but the biggest one is only .3uF @ 200v; I'd need 100+ to get up to 36 uF. I assume that more uF is okay but am wondering about new parts. I can get four 200v 10 or 15 uF "low impedance" electrolytic cap and fit time pretty easily on a slightly larger board ... is that going to do the job?

Thank you!

 - Ed.

[scottsAI]

Hi elt,

Sorry about the delay, did not see your reply until now.

No email address to send to get your attention sooner...

Bigger caps are fine. I mentioned the ATX supply because they're low ESR caps and are big uF, high voltage and current. And, I figured you had some!

You want a low ESR cap, the only reason I mentioned several was to get effective low ESR.

Yes - use: "The big ones are electrolytic, about 360uF 200v." One should do it.

If the cap is doing its job, it will be self limiting the voltage seen, my calculation limited the voltage to 40v so a 50v cap would be fine. Can you get 36uf or more at 50v?

How many will you be building?

If your like me I have several dead ATX supplies, looks like 2 big caps and bunch of little ones.

Hope this help!

Have fun,

Scott.

[elt]

Hi Scott,

I've done some low current tests with the new board; like before it works fine at lower power. I've only got two FETs at the moment so I have to wait a little before I go for full power.

I've posted a new schematic and artwork in the original thread.

(http://www.fieldlines.com/comments/2007/7/5/172519/4320/19?mode=alone;showrate=1#19)

Here's a picture -





I free-handed the slots for my current sensor with a little chip breaker bit. It didn't come out as nice as I dreamed but I can fix that up. (I won't add the current sensor though until last...)

I did have some 50v 10uF caps that I put on the board and I had a high-pulse cap I threw on there for good measure...

The pic also shows my "FET-driver chip" before I soldered it in (the small bread board on the right side.) I did ask for some MCP1407-E/AT samples but they say the lead time is 2 weeks and I'm impatient.

I did pull the big caps out of a PC power supply; those are hefty leads! I'm going to have to drill some bigger holes beore I put them in. The two 680uF caps only measure 480uF and 500uF; would that be a sign that they are showing their age? I'm guessing that the that computer was on 7x24 for three years, about 25,000 hours... I appreciate the offer for the caps very much but I'm thinking these'll be okay.

You asked:

> How many will you be building?

Well, at least one more; I'm already building my second mill! I might make more if I can find a bucket of nice Mosfets because I think having one controller per battery is the ultimate way to go.

 - Ed.

[scottsAI]

Hi elt,

Twice started a reply, busy around here. Now at the third time.

Full power is 43a, each FET is rated for 60a, the two can handle the power.

Heat may be another issue, bigger heat sink, try for short time with two, less to lose!

If using logic level MosFETs you do not need a gate driver, Micro has limited drive current helps slow things down just a bit. To slow it will add to the heat due to the time spent in the linear region. Slower rise times will reduce the wiring inductance effect. Every thing is a balance, a little time in the linear region will not hurt. Too fast switching, can also hurt, like the little wiring inductance hurt you.

Big caps often have +20, -80% cap accuracy!!

Generally a switching regulators will be better, values you have sound good.

One controller per battery?

How many batteries do you have? Maybe you should diagram your system ideas.

Have fun,

Scott.